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課程名稱 |
數位系統設計
Digital System Design |
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開課學期 |
100-1 |
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授課對象 |
資訊工程學系 |
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授課教師 |
甘宗左 |
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課號 |
CSIE3343 |
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課程識別碼 |
902 36500 |
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班次 |
02 |
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學分 |
3 |
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全/半年 |
半年 |
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必/選修 |
必帶 |
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上課時間 |
星期三6,7,8(13:20~16:20) |
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上課地點 |
資102 |
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備註 |
限學號雙號 且 限本系所學生(含輔系、雙修生) 且 限學士班三年級以上
總人數上限：80人 |
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課程簡介影片 |
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核心能力關聯 |
本課程尚未建立核心能力關連 |
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課程大綱
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為確保您我的權利,請尊重智慧財產權及不得非法影印
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課程概述 |
Introduction of Digital System Design
Number System
Combination Logic Design
K-MAP and QR Method for Logic Simplification
ALU Design
Multiplex, De-multiplex, Encoder and Decoder
Sequential Logic Design
State Machine Design
Pulse Generator and Signal Generator
Serial Computation and Communication Design
JTAG Introduction and Related Design
Simple CPU Design and Implementation
Verilog and VHDL Programming Design
FPGA Introduction and Design
Case Studies: OPENCORES Projects Study
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課程目標 |
The objective of this course is to introduce the student to various tools and paradigms for digital system design and to further their knowledge of the technical language used in this field. The focus of the course is at a level of abstraction that sits between high-level system specification issues and low-level system realization issues.
Topics covered include hardwired and stored logic paradigms for digital system implementation; the hardware description languages VHDL and Verilog, as a tool for modeling digital systems; a lab based introduction to configurable logic devices such as PLDs and FPGAs; system interconnection structures, including an introduction to bus arbitration schemes and data-link level bus communication protocols; architectural and operational aspects of general purpose central processing units (CPUs); an introduction to the use of programming languages (assembly and high-level) in the design of stored logic systems and related low-level issues such as the binding of program and data to memory; and memory and input/output organizations and interrupt mechanisms. |
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課程要求 |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
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參考書目 |
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評量方式
(僅供參考) |
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